SPIE AL 2020: Lithography-today-Challenges-and-solutions-across-a-diverse-market

SPIE AL 2020: Addressing-nanoimprint-lithography-mix-and-match-overlay-using-drop-pattern-compensation

SPIE AL 2020: Enabling-nanoimprint-simulator-for-quality-verification

SPIE AL 2020: Nanoimprint-system-alignment-and-overlay-improvements

SPIE AL 2020: Through-the-mask-TTM-optical-alignment-for-high-volume-manufacturing-nanoimprint-lithography-systems

SPIE AL 2019: Topography-and-flatness-induced-overlay-distortion-correction-using-resist-drop-pattern-compensation

SPIE AL 2019: Nanoimprint-system-alignment-and-overlay-improvement-for-high-volume-semiconductor-manufacturing

SPIE AL 2019: Patterning-mask-life-throughput-and-overlay-improvements-for-high-volume-semiconductor-manufacturing-using-nanoimprint-lithography

SPIE AL 2019: Status-of-overlay-performance-for-NIL-high-volume-manufacturing

SPIE AL 2019: The-advantages-of-nanoimprint-lithography-for-semiconductor-device-manufacturing

SPIE AL 2018: Nanoimprint-lithography-and-a-perspective-on-cost-of-ownership

SPIE AL 2018: A-novel-resist-system-for-enhanced-resist-spreading-in-nanoimprint-lithography

SPIE AL 2018: High-volume-semiconductor-manufacturing-using-nanoimprint-lithography

SPIE AL 2018: Improved-particle-control-for-high-volume-semiconductor-manufacturing-for-nanoimprint-lithography

SPIE AL 2018: Performance-of-a-nanoimprint-mask-replication-system

SPIE AL 2018: Progress-in-nanoimprint-wafer-and-mask-systems-for-high-volume-semiconductor-manufacturing

SPIE AL 2017: NIL for HVM memory

SPIE AL 2017: NIL systems

SPIE AL 2017: particle control

SPIE AL 2017: throughput

SPIE AL 2017: tone reversal

SPIE AL 2017: NIL overlay control

NIL defect performance toward High volume mass production

High resolution hole patterning with EB lithography for NIL template production

Design for nanoimprint lithography: Total layout refinement utilizing NIL process simulation

High Throughput Jet and Flash* Imprint Lithography for semiconductor memory applications

Nanoimprint System Development and Status for High Volume Semiconductor Manufacturing

Defectivity and Particle Reduction For Mask Life Extension, and Imprint Mask Replication For High Volume Semiconductor Manufacturing

Nanoimprint System Development and Status for High Volume Semiconductor Manufacturing

Hiroaki Takeishi, S. V. Sreenivasan

Alternative Lithographic Technologies VII, edited by Douglas J. Resnick, Christopher Bencher

Proc. of SPIE Vol. 9423, 94230C, 2015

Copyright 2015, Society of Photo-Optical Instrumentation Engineers. One print or electronic copy may be made for personal use only. Systematic reproduction and distribution, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.

doi: 10.1117/12.2087017

High throughput Jet and Flash Imprint Lithography for advanced semiconductor memory

NIL Template : progress and challenges

Defect Reduction for Semiconductor Memory Applications Using Jet And Flash Imprint Lithography

Defect reduction for semiconductor memory applications using jet and flash imprint lithography

Effects of Cleaning on NIL Templates: Surface Roughness, CD and Pattern Integrity

Mask replication using jet and flash imprint lithography

Defect reduction of high-density full-field patterns in jet and flash imprint lithography

Technology review and assessment of nanoimprint lithography for semiconductor and patterned media manufacturing

Nanoimprint lithography and future patterning for semiconductor devices

Development of Template and Mask Replication Using Jet and Flash Imprint Lithography

Cleaning of step-and-flash imprint masks with damage-free nonacid technology

Inspection of Imprint Lithography Patterns for Semiconductor and Patterned Media

Inspection of 32nm imprinted patterns with an advanced e-beam inspection system

High-Resolution E-Beam Repair for Nanoimprint Templates

Progress of UV-NIL Template Making

Defect inspection of imprinted 32 nm half pitch patterns

Development status of back-end process for UV-NIL template fabrication

UV NIL template making and imprint evaluation

Evaluation of E-Beam Repair for Nanoimprint Templates

Full field imprint masks using variable shape beam pattern generators

Step-and-Flash Imprint Lithography for Storage-Class Memory

Controlling Linewidth Roughness in Step and Flash Imprint Lithography

32 nm imprint masks using variable shape beam pattern generators

UV NIL mask making and imprint evaluation

Dual Damascene BEOL processing using multilevel step and flash imprint lithography

Etching of 42 nm and 32 nm Half-Pitch Features Patterned Using Step and Flash® Imprint Lithography

Full field imprinting of sub-40 nm patterns

Study of nanoimprint applications toward 22nm node CMOS devices

Defect Reduction Progress in Step and Flash Imprint Lithography

The Development of Full Field High Resolution Imprint Templates

Patterned Wafer Defect Density Analysis of Step and Flash Imprint Lithography

UV Nanoimprint Tool and Process Technology

Materials for step and flash imprint lithography

Minimizing Linewidth Roughness in Step and Flash Imprint Lithography

Nanoimprint applications toward 22nm node CMOS devices

Lithography Beyond 32nm – A Role for Imprint?

Toward 22 nm for unit process development using step and flash imprint lithography

A Study of Imprint-Specific Defects in the Step and Flash Imprint Lithography Process

Step and Flash Imprint Lithography Templates for the 32 nm Node and Beyond

Defect Inspection for Imprint Lithography Using a Die to Database Electron Beam Verification System

Materials Today

Effects of etch barrier densification on step and flash imprint lithography

Advanced Mask Metrology Enabling Characterization of Imprint Lithography Templates

S-FIL Technology: Cost of Ownership Case Study

Indium Tin Oxide Template Development for Step and Flash Imprint Lithography

Development of an Etch-definable Lift-off Process for Use with Step and Flash Imprint Lithography

Fabrication of Nanometer Sized Features on Non-Flat Substrates Using a Nano-Imprint Lithography Process

Initial study of the fabrication of step and flash imprint lithography templates for the printing of contact holes

Image placement issues for ITO-based step and flash imprint lithography templates

Inspection of templates for imprint lithography

Repair of step and flash imprint lithography templates

Distortion and Overlay Performance of UV Step and Repeat Imprint Lithography

Development of Imprint Materials for the Step and Flash Imprint Lithography Process

Evaluation of the Imprio 100 Step and Flash Imprint Lithography Tool

Imprint lithography for integrated circuit fabrication

Step and flash imprint lithography template characterization, from an etch perspective

Design and Performance of a Step and Repeat Imprinting Machine

Employing Step and Flash Imprint Lithography for Gate Level Patterning of a MOSFET Device

Advances in Step and Flash Imprint Lithography

Imprint Lithography: Lab Curiosity or the Real NGL?

Analysis of critical dimension uniformity for step and flash imprint lithography

Fabrication of Step and FlashTM Imprint Lithography Templates Using Commercial Mask Processes

Nano-imprint lithography edges toward sub-50-nm feature sizes for integrated circuits.

Critical Dimension and Image Placement Issues for Step and Flash Imprint Lithography Templates

High resolution templates for step and flash imprint lithography

Hydrogen silsesquioxane for direct electron-beam patterning of step and flash imprint lithography templates

Characterization of and imprint results using indium tin oxide-based step and flash imprint lithography templates

Prediction of fabrication distortions in step and flash imprint lithography templates

Template fabrication schemes for step and flash imprint lithography

Low-Cost Nanostructure Patterning Using Step and Flash Imprint Lithography

Release Layer Study

High Resolution Templates for Step and Flash Imprint Lithography

Design of Orientation Stages for Step and Flash Imprint Lithography

Characterization and modeling of volumetric and mechanical properties for step and flash imprint lithography photopolymers

Step and flash imprint lithography: Defect analysis

Layer-to-Layer Alignment for Step and Flash Imprint Lithography

New Methods for Fabricating Step and Flash Imprint Lithography Templates

Partially Constrained Compliant Stages for High Resolution Imprint Lithography

Step and flash imprint lithography: Template surface treatment and defect analysis

Step and flash imprint lithography for sub-100nm Patterning

Patterning curved surfaces: Template generation by ion beam proximity lithography and relief transfer by step and flash imprint lithography

Step and Flash Imprint Lithography: A New Approach to High Resolution Patterning