J-FIL for the Semiconductor Market
Tools that Advance Moore’s Law
Since its inception nearly 50 years ago, the semiconductor industry has utilized optical lithography to print ever-shrinking patterns on silicon wafers, thereby creating devices such as microprocessors and NAND Flash memory with ever increasing transistor densities. For the last two decades, lithographers have predicted the demise of optical lithography because of its presumed inability to print features smaller than the wavelength of light, leading to development of so-called next generation lithography (NGL) technologies such as extreme ultraviolet (EUV), hard X-ray, E-beam direct write (EBDW) or maskless, E-beam projection lithography (EPL), ion beam projection lithography (IPL) and 157nm. Each were designed to displace optical lithography but required costly new infrastructures, including new source, resist and photomask technologies, and have not proven to be economically or technically viable.
Presently, the industry uses 193 immersion lithography, which means lithographically, there is no way to directly pattern features with a half pitch smaller than 40nm. Pitch reductions are now accomplished through a combination of 193i and self-aligned spacer double patterning (SADP) for half pitches down to 20nm and 193i and self-aligned spacer quadruple patterning (SAQP) for half pitches below 20nm. While in many cases this has allowed the industry to continue to scaling, there have been three alarming trends resulting from the pitch limitation described above:
- SADP and SAQP processes are one dimensional patterning solutions which severely restrict design layouts.
- The additional processing required (which includes many extra lithography, deposition and etch steps) after the primary lithography adds significant cost to every wafer processed.
- We are not keeping up with Moore’s Law, meaning while the cost of lithography rises, our ability to scale cannot match the trends established for the last 25 years.
A J-FIL technology that can directly image the pattern of interest without additional processing extends the semiconductor roadmap, substantially reduces cost and eliminates the stringent design rule restrictions present for many leading edge device architectures.
Canon Nanotechnologies understands the semiconductor industry’s drive to continue to produce ever-shrinking features on silicon and has crafted its technology to leverage the existing optical lithography infrastructure, while providing a direct patterning solution. Jet and Flash Imprint Lithography (J-FIL) technology utilizes readily available I-line sensitive photoresist and source technology. Because J-FIL does not use sub-wavelength lithography that depends on the transfer of an aerial image, circuit designers are freed from restricted design rules (RDR) and complex optical proximity correction (OPC).
In addition, J-FIL masks can be purchased from commercial mask makers such as Dai Nippon Printing, which use their existing photomask manufacturing lines to produce imprint masks. Canon Nanotechnologies is cooperating with manufacturers of mask and template writing tools, repair and inspection tools, and mask blank materials producers to help insure the reliability of the imprint mask supply chain.
All of Canon Nanotechnologies’ nanoimprint lithography systems are based on its core technology, Jet and Flash Imprint Lithography (J-FIL). Current systems include the Imprio 450 wafer processing system and the MR5000 mask replication system.